The present disclosure relates to a comparator, a single-slope analog-to-digital (hereinafter referred to as an AD) converter, a solid-state imaging device represented by a CMOS image sensor, a camera system, and an electronic apparatus.
In recent years, attention has been paid to CMOS (Complementary Metal Oxide Semiconductor) image sensors as solid-state imaging devices (image sensors) instead of CCDs (Charge Coupled Devices) for the following reason.
As for the CCDs, it is necessary to take a dedicated process to manufacture CCD pixels, use a plurality of power supply voltages to operate the CCD pixels, and operate the CCD pixels in combination with a plurality of peripheral ICs (Integrated Circuits).
On the other hand, the CMOS image sensors address various problems such as a highly-complicated system of the CCDs. For this reason, the CMOS image sensors have received the attention.
In manufacturing a CMOS image sensor, it is possible to use the same manufacturing process as that of a general CMOS integrated circuit. In addition, it is possible to drive the CMOS image sensor with a single power supply. Moreover, it is possible to mix together an analog circuit and a logic circuit using a CMOS process in the same chip.
Therefore, the CMOS image sensor brings about a plurality of great advantages such as a reduction in the number of peripheral ICs.
In the output circuit of a CCD, a single channel (ch) output using a FD (Floating Diffusion) amplifier with a FD layer is in the mainstream.
On the other hand, the CMOS image sensor has a FD amplifier for each pixel. As an output of the CMOS image sensor, a column-parallel output is in the mainstream where the CMOS image sensor selects one of the rows of a pixel array and simultaneously reads the same in a column direction.
This is because parallel processing is advantageous due to the fact that it is difficult to obtain sufficient drive performance with the FD amplifiers arranged in the pixels and thus necessary to reduce a data rate.
As a signal output circuit of the column-parallel output CMOS image sensor, various types have been proposed.
As a method of reading a pixel signal in the CMOS image sensor, there has been known a method where a signal charge serving as a light signal generated by a photoelectric conversion device such as a photodiode is temporarily sampled by a capacitance via a MOS (Metal-Oxide Semiconductor) switch arranged near the photoelectric conversion device and then read.
In a sampling circuit, noise having an inverse correlation is generally caused in a sampling capacitance value.
In transferring a signal charge to a sampling capacitance, a pixel uses a potential slope to completely transfer the signal charge. Therefore, the noise is not caused in the sampling process but is caused when a voltage level of a previous capacitance is reset to a certain reference value.
As a general method of eliminating noise, CDS (Correlated Double Sampling) has been known. In this method, a signal charge in a state immediately before its sampling (reset level) is once read and stored, and then a signal level after the sampling is read and subtracted from the reset level to eliminate the noise.
Specific methods of the CDS include various techniques.
In addition, as a pixel signal reading (outputting) circuit of the column-parallel output CMOS image sensor, various types have been proposed. Among them, the most advanced type is a circuit that includes an AD converter (hereinafter referred to as an ADC) for each column and fetches a pixel signal as a digital signal.
The CMOS image sensors having such column-parallel ADCs are disclosed in, for example, “An Integrated 800×600 CMOS Image system” (ISSCC Digest of Technical Papers, pp. 304-305, February, 1999, by W. Yang et. al), Japanese Patent Application Laid-open No. 2005-278135, Japanese Patent Application Laid-open No. 2005-295346, and Japanese Patent Application Laid-open No. 63-209374.